A local approach to buildings by Tits J.

By Tits J.

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Agrawal, and S. K. Jain, "A gatelevel model for CMOS combinational logic circuits with application to fault detection," in Proc. , Albuquerque, NM, pp. 504-509, June 1984. [REDD86] S. M. Reddy and M. K. Reddy, "Testable realizations for FET stuck-open faults in CMOS combinational logic circuits," IEEE Trans. , vol. 0-35, pp. 742-754, Aug. 1986. [SHEN85] J. P. Shen, W. Maly, and F. J. Ferguson, "Inductive fault analysis of MOS integrated circuits," IEEE Design fj Test, vol. 2, no. 6, pp. 13-26, Dec.

LEVI81] M. W. Levi, "CMOS is most testable," in Proc. Int. , Philadelphia, PA, pp. 217-220, Oct. 1981. -H. Lu, "Implementation of iterative networks with CMOS differential logic," IEEE J. Solid-State Circuits, vol. 23, no. 4, pp. 1013-1017, Aug. 1988. [MALA82] Y. K. Malaiya and S. Y. H. Su, "A new fault model and testing technique for CMOS devices," in Proc. Int. , Philadelphia, PA, pp. 25-34, Oct. 1982. [MALA84] Y. K. Malaiya, "Testing stuck-on faults in CMOS integrated circuits," in Proc. Int.

Thus by just looking at the output it is not possible to find out which s-arl fault is present. Faults like these which can not be distinguished are said to be equivalent. Similarly, we can see that all the s-arO faults in an AND gate are equivalent. For a NOR (NAND) gate the set of equivalent faults consists of all the input s-a-l (s-arO) faults and the output s-a-O (s-a-l) fault. Only one of the faults from the set of equivalent faults needs to be considered for test generation purposes. Another way of reducing the number of faults that need consideration is through the use of the concept of fault dominance.

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